Regviz

NXP Semiconductors /LPC176x5x /WDT /MOD

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MOD

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC176x5x/WDT/MOD#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STOP)WDEN 0 (NORESET)WDRESET 0 (WDTOF)WDTOF 0 (WDINT)WDINT 0RESERVED

WDRESET=NORESET, WDEN=STOP

Description

Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.

Fields

WDEN

Watchdog enable bit. This bit is Set Only.

0 (STOP): The watchdog timer is stopped.

1 (RUN): The watchdog timer is running.
WDRESET

Watchdog reset enable bit. This bit is Set Only. See Table 652.

0 (NORESET): A watchdog timeout will not cause a chip reset.

1 (RESET): A watchdog timeout will cause a chip reset.
WDTOF

Watchdog time-out flag. Set when the watchdog timer times out, cleared by software.
WDINT

Watchdog interrupt flag. Cleared by software.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data